The present disclosure relates to computer-aided testing for design verification of integrated circuits, and more particular a method for automated generation of test layouts for verification of design rule checking decks.
Design Rule Checking (DRC) is an area of Electronic Design Automation (EDA) that is used to determine whether the layout design of an integrated circuit satisfies a series of recommended parameters called design rules. Due to the complexity and sheer number of circuit parts in a typical integrated circuit, the DRC process is typically performed using CAD software or more specifically DRC software. An example of DRC software is Calibre® by Mentor Graphics®. Typically, the design rules are specific to a particular manufacturing process and may specify for example certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in the manufacturing processes. A set of design rules for a particular process is referred to as a DRC deck, DRC run-set, or rule deck. A typical DRC deck may include instructions for the running of several hundred to thousands of design rule checks. For example, a DRC deck may comprise a command language input file that instructs a processor how to execute the design rule checks on a layout design file defining polygon shapes representing an integrated circuit to be manufactured.
In order to verify an implementation of a DRC deck, a collection of test layouts is needed consisting of cases one expects to pass the design rule check—the so-called ‘pass cases’, and cases one expects to fail the design rule check—the so-called ‘fail cases’. For instance, if it is desired to test whether a certain requirement (constraint) of a design rule is implemented correctly, it is useful to generate at least one fail case and at least one pass case for that requirement. However, because the number of valid topologies of the edges and shapes featuring in a design rule deck grows very rapidly with their number, as does the number of combinations of parameter values, it will be appreciated that the amount of test layouts or patterns can get exceedingly large. Manual generation of test layouts is limited by the imagination, expertise, and diligence of the person tasked with creating the layouts. Accordingly, it is desired to generate the test layouts automatically using a computer.
For example, U.S. Pat. No. 8,875,064, describes automated design rule checking (DRC) test case generation, wherein the method includes extracting coordinates of an error marker in an integrated circuit design, creating an error polygon using the coordinates, selecting polygons in the design that touch the error polygon, identifying a rectangle that encloses the selected polygons, and generating a test case based on data of the design contained within the rectangle. Unfortunately, the known method relies on error markers in an integrated circuit design which may not be adapted to cover the rules of a specific DRC deck.
Accordingly, it is desired to improve automatic generation of test layouts for verifying a DRC deck, in particular to provide test layouts that are of particular relevance for checking the DRC deck.